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Questions in design

What is the relation with jitter and phase noise?
Phase noise and jitter are two different descriptions to the same phenomenon. Jitter is a concept of time domain, the unit is pS or fS; phase noise is the concept of frequency domain, it is the ratio of the rectangular area at 1Hz bandwidth of offset frequency fm with the area contained in the whole power spectrum curve, the unit is expressed in -dBc/Hz..
What’s the function of voltage referential terminal of OCXO?

Usually the clock board requires a high accuracy voltage reference, the solution is to add a high accuracy voltage reference chip on the clock design, but this will cost-up the clock. Another solution is to obtain the voltage reference from the voltage reference terminal of OCXO. Since the voltage reference OCXO is usually placed in a constant temperature of the place, and OCXO accuracy of the thermostat bath temperature is usually 0.1℃, so it further mitigates the voltage reference sensitivity to temperature change. It is always recommended to take OCXO voltage reference terminal as the clock voltage reference.

Please note the load current at voltage referential terminal should be less than 1mA.

Does voltage control ripple affect stability of crystal oscillator?
If the controlled voltage of crystal oscillator is changed, the frequency will follow to change. When the interference signal is too strong, it would cause Jittering or deterioration of phase noise, and even frequency change. Usually, a low-pass filter loop circuit with a frequency response more than 2KHz is designed, at the voltage-controlled terminal of crystal oscillator internally, so as to reduce the external ripple interference at the voltage-controlled terminal. In case there’s a strong external interference in the working environment, a low-pass filter can also be added to the voltage-controlled terminal externally.
What issues to be noted for power system design of crystal oscillator?

To jumper a 10~100uF tantalum capacitor or ceramic capacitor at the power input terminal of crystal oscillator, if the power supply voltage is lower, or PCB wiring is getting thinner, the capacitance of capacitor should be increased respectively so as to decrease the ripple interference. In addition, at the power input of crystal oscillator, a 0.01uF ceramic decoupling capacitor should also be jumpered, we recommend the way of "connection on the same layer", it mustn’t be connected through the hole in the power supply layer and the ground layer.

As for OCXO product, the power of supply system must be greater than the startup power of OCXO, and reserve a certain of excess. 

    

                               OCXO                                                               TCXO/MCXO/VCXO/OSC 

 
                              Sinewave                                                                      Square Wave                        

        
               Clipped Sinewave                                                 (LV)PECL

What issues must be noted for clock system PCB layout?

In considering of PCB layout, the basic principle follows as:
Try to avoid input line and output line adjacent in parallel of generating reflection interference
To consider the noise originated from the power and ground cables, add a decoupling capacitance, to widen the power supply and ground cables; The width of cable is accordance with the rule: Ground cable> Power cable> Signal cable, and try to use large area copper layer as ground cable.
To consider signal cross-interference, keep it away from the ground line, remove the cross-interference or shield the interference signal.
Try to assure of integrity of the ground layer

In consideration of layout:
Try to solder the crystal oscillator on PCB as far as possible, reduce use of DIP as possible;
Try to keep the high-frequency signal line as possible away from the sensitive analog circuit devices
Try to keep a terminal grounded for connection of digital ground and analog ground, or connect through an external interface (eg. socket).

Where is the best place for the crystal oscillator in the equipment?
As the main factor to affect the short-term stability of the crystal oscillator is temperature change, in considering of the overall configuration, try to avoid the crystal oscillator near the chassis enclosure as far as possible or near the parts such as fans which change temperature much, also it shoud be far away from the high-power RF devices such as RF power amplifier. In circumstances of vibration or acceleration variation, the bearing capability of crystal oscillator must be considered to assure of stress distribution evenly, and to take effective measures to reduce vibration and so on.
Does power ripple effect crystal oscillator?
Usually, the requirement for the power supply ripple and noise is less than 1% of the output voltage, as crystal oscillator has an accurate reference voltage internally, its ripple suppression, load regulation is very excellent, the accuracy can reach 3ppm/℃. The interference to the crystal oscillator of the ripple less than 1% for the power system can be ignored.
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